D3.2 - Standard cell lib. Representing various design corners in the design environment

In order to explore the opportunities of SOT-based memories at architectural level, a library of primary SOT-based logic and memory elements should be developed and characterized. Synthesis tools such as Synopsis Design Compiler can then utilize the resulting libraries to synthesize higher level design descriptions into the logic and memory cells included in the library file. The .lib file format is used to represent the timing and power characteristics of each library cell in the ASCII format. The timing and power values are obtained by simulating each cell under various conditions. In this report, the design and characterization procedure of SOT-based cells in the scope of the SpOt project (D3) is detailed. As a case study, the design and structure of a Non-Volatile Flip-Flop (NVFF) is presented. Télécharger le document

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