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ASIC digital designer position (CLOSED)

An ASIC digital designer position is proposed, for a period of 12 months within the CNRS-CEA SPINTEC laboratory. A solid knowledge of digital design techniques, synthesis and Place and Route is required for this position, as well as knowledge of processor architectures. Since the global target is a low-power ASIC, knowledge in clock and/or power gating would be also appreciated. The full poposition is available here. Télécharger le document

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spin Orbit torque memory for cache & multicore processor applications

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