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A 3-terminal based integrated circuit submitted for fabrication

An hybrid CMOS/MRAM integrated circuit based on the 3-terminal SOT device has been designed and submitted for fabrication on July 15th.

spOt-Circuit
spOt Events & Results

In the framework of the European spOt project, an hybrid CMOS/MRAM integrated circuit based on the 3-terminal SOT device has been designed and submitted for fabrication on July 15th. The CMOS process is the 130nm from STMicroelectronics and the MRAM-SOT post-process will be managed by LETI on Q1 2015 on their specific equipment.

This ASIC embeds several blocks, such as a full SOT memory including all the peripherals (decoders, level shifters, pulse generator, sense amplifiers...). It also embeds some logic blocs such as latches and flip-flops, non-volatile counter and shift register.

Finally, a complete set of characterization structures used to extract post-process electrical data from wafer tests is also integrated to this ASIC. The aim of this silicon demonstrator is twofold:

  1. to prove the concept and feasibility of such a functional hybrid CMOS-SOT integrated circuit
  2. to fabricate a very fast (<ns) non-volatile SOT-MRAM to target e.g. SRAM-cache replacement.

Test and characterization results are expected for Q2 2015.

spin Orbit torque memory for cache & multicore processor applications

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