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Fabrication of the first spOt Memory test chips

The first fabrication run of our hybrid CMOS/SOT-MRAM just finishes and the first spOt Memory test chips are now ready to be tested.

spOt-Circuit_design
spOt Events & Results

The first fabrication run of our hybrid CMOS/SOT-MRAM just finishes and LETI delivered the first spOt wafers with hybrid CMOS/SOT-MRAM circuits.

Based on the results gathered by our consortium in terms of magnetic stacks optimization, single cell characterization, design environments development, ... a simple memory array was designed as proof of concept. This array includes a full memory with amplifiers, drivers and addressing schemes. The test chips were designed, simulated and verified using the design tools developed in WP3 in a CMOS-compatible process.

These spOt circuits were submitted to MPW fabrication with the ST130nm CMOS technology. Magnetic stacks were deposited by SINGULUS Technology and the LETI processed the wafers. 

The circuits are now ready to be packaged and then tested at SPINTEC.

spin Orbit torque memory for cache & multicore processor applications

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