The spOt Background

The microelectronics industry will face major challenges related to power dissipation and energy consumption in the next years. Both static and dynamic consumption (already dominated by the leakage power) will soon start to limit microprocessor performance growth. Multicore processors e.g. will not be able to afford keeping more than a very small fraction of all cores active at any given moment and their scaling will soon hit a power wall.

A promising way to stop this trend is integration of non-volatility as a new feature of memory caches, which would immediately minimize static power as well as paving the way towards normally-off/instant-on computing. The development of an electrically addressable NVM combining high speed and high endurance is essential to achieve these goals.

Among the recent emerging memories, Spin Transfer Torque Magnetic Random Access Memory has been identified by the ITRS as the most credible candidate. However STT-MRAM still suffers from a lack of speed for cache application and from potential endurance issues due to the large current injected through the tunnel barrier for switching the magnetization.

spin Orbit torque memory for cache & multicore processor applications

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