The spOt breakthrough

The goal of the project is to introduce non-volatile fast memories in the core of the processors in order to develop a new class of power efficient and scalable microprocessors.

To accomplish this aggressive goal, limitations of present non-volatile memories in terms of speed and endurance must be overcome and new architectures taking full benefit of these new functionalities must be developed. Would it succeed, it would imply a comprehensive modification of the memory hierarchy leading to a large reduction of power consumption and thermal dissipation.

To tackle these issues the consortium will base its research on a recent discovery achieved jointly by Spintec and the Catalan Institute of Nanotechnology (ICN), which is called “Spin Orbit Torque” (SOT). This disruptive technology, which can be viewed as the ultimate evolution of STT, offers the same non-volatility and compliance with technological nodes below 22nm, with the addition of lower power consumption, cache-compatible high speed, and truly infinite endurance. Proof of principle has already been demonstrated on isolated cells with switching speed <0.5ns.

Comparison of standard cell for STT (left) and SOT (right)

Comparison of standard cell for STT (left) and SOT (right)

In order to demonstrate its viability for cache, a number of identified technology roadblocks must be addressed:

  • A magnetic stack presenting both large SOT (for write) and large Tunnel Magneto-Resistance (for read) must be developed,
  • Writing current needs to be lowered to match advanced transistor outputs,
  • The cell architecture must be optimized to accommodate the 3-terminal geometry,
  • Novel system level architectures combining logic and memory must be developed, in particular with an increased granularity of the memory within the processors.

The spOt project intends to pave the way to improved processors capabilities in terms of energy consumption and thermal dissipation allowing for example many more active cores under a fixed power budget than a pure CMOS implementation could afford. 

spin Orbit torque memory for cache & multicore processor applications

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