The spOt objectives

The final objective of the project is twofold: The fabrication of a SOT memory test chip, which would be benchmarked against existing and forecasted solutions (in particular state-of-the art STT-MRAM), in order to demonstrate the integrability and manufacturability of this new technology; The design and full chip simulation of a novel multicore processor integrating embedded SOT memory, in order to demonstrate the systemability of such approach.

spOt is organized in 5 work-packages and has 4 intermediate goals:

  1. the realization of a fast write, low power, high read signal single memory cell
  2. the development of a single cell architecture (standard cell) with minimal footprint
  3. A stand-alone memory test chip with full functionality
  4. The full chip simulation of a low-power/normally-off multicore processor.

The project is prospective and risky but with outstanding potential. When completed, it will lead to viable disruptive and highly competitive technologies for the next decade products.

Several demonstrators will validate spOt’s results at the end of the day:

  • A SOT memory test chip will be fabricated in order to demonstrate the integrability and manufacturability of this new technology (T0+36),
  • Jointly with a simulated full chip of a novel multicore processor integrating embedded SOT memory, in order to demonstrate the systemability of such approach (T0+36),
  • Completed by key device SOT simulation software dedicated to the growing spintronics industry (T0+36).

spin Orbit torque memory for cache & multicore processor applications

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