Work Package 4 - Hybrid Architecture for Systemability

This work package consisted in the design of hybrid architecture based on the SOT-MRAM concept. It aimed at exploring and demonstrating the benefits of this technology to achieve dense, high performance, low power and resilient architecture while providing systemability and integrability. Its objectives were:

  • To develop high-level architectural simulation models and tools for hybrid CMOS-magnetic systems
  • To develop techniques for architecture design so as to demonstrate SOT benefits (dense, high performance, low power, resilient) while providing systemability and integrability
  •  To provide design for manufacturability (DfM) techniques to increase yield and reliability 

Work Package structure

To reach these objectives, this work package led by KIT, has been divided in 4 tasks in which the different partners will work in close collaboration.

Multi-level simulator

KIT and Spintec have developed a hierarchical simulation framework capable of experimenting with various architectural design parameters and an FPGA emulator engine to be able to handle full chip simulation.

Hybrid architecture design

KIT and Spintec have explored the scaling of this memory technology and architectural issues considering various architectures based on SOT, MTJ and CMOS.

Design for Manufacturability

KIT, InSilicio and the Advisory Board have studied the impact of process variations on SOT memories and developped circuit and architecture design techniques that can improve manufacturing yield and reliability. 

Full-chip simulation

KIT and the Advisory Board have finally simulated a full chip multicore architecture with hybrid and heterogeneous SOT-based memory hierarchy. 

For more information on these achievements, please contact Dr. Gilles Gaudin, spOt project coordinator.

spin Orbit torque memory for cache & multicore processor applications

Private space

Menu principal