Work Package 5 - Memory test chip design/fab for Integrability and Manufacturability

This work package consisted in the design, simulation and fabrication of a memory array chip as a proof of concept. Functional tests have been performed to evaluate the memory demonstrator. The objectives were:

  • To design of a simple memory array
  • To nanofabricate a SOT memory test chip 
  • To characterize the memory chip and  validate the SOT technology
  •  To simulate process variability impact on performances and propose manufacturing friendly designs

Work Package Structure

To reach these objectives, this work package led by LETI, was divided in 4 tasks in which the different partners will work in close collaboration.

Test Chip design

KIT, Spintec and LETI have fabricated an SOT memory test chip. The chip has been designed, simulated and verified using the design tools developed in WP3 in a CMOS-compatible process.

Test Chip Fabrication

LETI, KIT and Singulus have fabricate a hybrid CMOS/SOT circuits. 

Memory characterization

SPINTEC, LETI and the Advisory Board have tested the fabricated memory demonstrator. The test will be mainly functional. 

Simulation for Manufacturability

InSilicio and LETI have set up magnetic cell models to support anticipated process variability of various types and simulated process variability impact on performances. 

For more information on these achievements, please contact Dr. Gilles Gaudin, spOt project coordinator.

spin Orbit torque memory for cache & multicore processor applications

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